picchick - blob - git.mckinnon.ninja

picchick
A utility to aid in programming PIC microcontrollers
picchick
tests
xc8-pic-16f1454.ini
# Generated 05/12/2024 GMT

# Copyright © 2024, Microchip Technology Inc. and its subsidiaries ("Microchip")
# All rights reserved.
# 
# This software is developed by Microchip Technology Inc. and its subsidiaries ("Microchip").
# 
# Redistribution and use in source and binary forms, with or without modification, are
# permitted provided that the following conditions are met:
# 
#     1. Redistributions of source code must retain the above copyright notice, this list of
#        conditions and the following disclaimer.
# 
#     2. Redistributions in binary form must reproduce the above copyright notice, this list
#        of conditions and the following disclaimer in the documentation and/or other
#        materials provided with the distribution. Publication is not required when
#        this file is used in an embedded application.
# 
#     3. Microchip's name may not be used to endorse or promote products derived from this
#        software without specific prior written permission.
# 
# THIS SOFTWARE IS PROVIDED BY MICROCHIP "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL MICROCHIP BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING BUT NOT LIMITED TO
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWSOEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

#	PICC.INI
#	This file defines the memory sizes and organization
#	of a PIC10/12/16 device
#
#	All values are in hexadecimal unless otherwise stated.
#
#	Fields used are:
#
#	ARCH=<processor_architecture>
#			PIC12, PIC14 or PIC16, corresponding to baseline,
#			midrange and high end respectively
#	PROCID=<id>
#			Microchip processor identifier. This corresponds
#			to the processor field in Microchip COFF output.
#	ROMSIZE=<size_of_rom>
#			Size of program memory (words) in hex
#	BANKS=<num_banks>
#			Number of data memory banks used (for the
#			midrange, this will always be at least 2)
#	RAMBANK=<range_start>,<range_end>
#			This field may appear multiple times and
#			specifies a RAM bank memory range. e.g. A0,BF
#	COMMON=<range_start>,<range_end>
#			Specifies an area of RAM that is mirrored in all
#			banks, i.e. is accessible regardless of RPn settings.
#	ICD1RAM=<range_start>,<range_end>
#			Specifies an area of RAM that is used by
#			MPLAB-ICD
#	ICD2RAM=<range_start>,<range_end>
#			Specifies an area of RAM that is used by
#			MPLAB-ICD2
#	ICD3RAM=<range_start>,<range_end>
#			Specifies an area of RAM that is used by
#			MPLAB-ICD3 and REAL-ICE
#	ICD1ROM=<range_start>,<range_end>
#			Specifies an area of ROM that is used by
#			MPLAB-ICD
#	ICD2ROM=<range_start>,<range_end>
#			Specifies an area of ROM that is used by
#			MPLAB-ICD2
#	ICD3ROM=<range_start>,<range_end>
#			Specifies an area of ROM that is used by
#			MPLAB-ICD3 and REAL-ICE
#	DATABANK=<bank>
#			Identifies which bank the EEDATA/PMDATA register is found.
#			Used for library selection.
#
#	FLASHTYPE=<string>
#			Indicates if and how this midrange processor is capable of reading
#			and how a device can write to its own program memory.
#			READ - Read only
#			READWRITE_1 - Writes one word at a time, erasure is automatic
#			READWRITE_A - Writes done in blocks of words, block erasure automatic
#			READWRITE_B - Writes done in blocks, erasure is separate step
#
#	FLASH_READ=<size>
#			The number of words read in a flash-read operation. Default is zero.
#
#	FLASH_WRITE=<size>
#			The number of words in flash writing block. Default is zero.
#
#	FLASH_ERASE=<size>
#			The number of words in a flash-erase block. Default is FLASH_WRITE size.
#
#	EEPROM=<range_start-range_end>
#			Identifies the range (bytes) of EEPROM available to this device
#
#	FLASHDATA=<range_start-range_end>
#			Defines the range of flash memory used to access EEPROM data
#
#	OSCCAL=<address>
#			The address where the OSCCAL sfr is located.
#
#	OSCCON=<address>
#			The address where the OSCCON sfr is located.
#
#	OSCHOW=<string>
#			How does the device calibrate its oscillator?
#			RETLW - The device's oscillator calibration constant is stored at the top
#			of program memory in a RETLW instruction, the compiler can assign this
#			to the OSCCAL sfr which is located at OSCCAL.
#			CALWORD - The device stores the oscillator constant in a calibration
#			word located in flash program memory.  The word is read from program
#			memory and assigned to OSCCAL.  The compiler does not perform this
#			operation.  It must be done by the user's program.
#
#	CONFIG=<range_start-range_end>
#			Define a new address range for the configuration register region if
#			the address range differs from the traditional range for its
#			architecture type.
#
#	IDLOC=<range_start-range_end>
#			Define a new address range for the user ID location region if
#			the address range differs from the traditional range for its
#			architecture type.
#
#	STACKDEPTH=<limit>
#			This is used set the maximum stack level depth for a processor. If not specified,
#			the default setting will be 2 for baseline PICs, 8 for midrange PICs and 16 for
#			high-end PICs and enhanced mid-range PICs.
#
#	VOLSFRS=<range_start>-<range_end>,...
#			Instructions generated by the compiler that access SFRs in the given memory
#			ranges will won't be optimized by the assembly optimizer
#
#	BANKSIZE=<size>
#			Maximum number of bytes in a RAM bank.
#
#	PAGESIZE=<size>
#			Maximum number of words in a program memory page.
#
#	LINEARBASE=<addr>
#			Base address of the virtual linear data memory, exclusive to enhanced mid-range devices.
#
#   PCBITS=<number of bits>
#           How many implemented bits are there in the PC?
#
#   EEADRBITS=<number of bits>
#           How many bits are available to address data EEPROM, if any.
#
#   BANKSELBITS=<number of bits>
#           Number of bits available for bank-selection.
#
#   EEPROMINT=<EEREG_INT|NVMREG_INT>
#   		Which register interface is used to access the device's EEPROM, if any.
#
#	SFR=<name>,<address>,<bit-width>
#			Describes a SFR of the device.  The address is in hexadecimal, and the bit-width decimal.
#			SFRs are sorted in order of address, and then by bit-width in descending order.  If an SFR duplicates
#			an address, then that SFR is an alias of the first with that address.  An SFR that has a bit-width
#			greater than the next, but the next also shares the same address, then that SFR is a joined SFR
#			of those that follow, but limited by its bit-width.
#
#	SFRFLD=<name>,<address>,<bit-position>,<bit-width>
#			Describes a SFR bit-field of the device.  The address is in hexadecimal, and the bit-width and
#			bit-position are decimal. SFRFLDs are sorted in order of address.
#
#	CONFIGPROG=<num_regs>,<delta>,<alignment>
#	IDLOCPROG=<num_regs>,<delta>,<alignment>
#			These describe the programming characteristics of configuration and user id memory.
#			Where,
#			<num_regs> = the number of registers (equivalent to a CWORD in CFGDATA files) per programming unit.
#			<delta> = the address delta between contiguous registers, i.e. the addresses of a CWORD.
#			<alignment> = the address alignment of programming units, where the address is that of the first CWORD
#							in the programming unit.
#

[16F1454]
ARCH=PIC14E
BANKS=20
BANKSELBITS=0x5
BANKSIZE=0x80
COMMON=70-7F,F0-FF,170-17F,1F0-1FF,270-27F,2F0-2FF,370-37F,3F0-3FF,470-47F,4F0-4FF,570-57F,5F0-5FF,670-67F,6F0-6FF,770-77F,7F0-7FF,870-87F,8F0-8FF,970-97F,9F0-9FF,A70-A7F,AF0-AFF,B70-B7F,BF0-BFF,C70-C7F,CF0-CFF,D70-D7F,DF0-DFF,E70-E7F,EF0-EFF,F70-F7F,FF0-FFF
CONFIG=8007-8008
CONFIGPROG=1,1,1
DATABANK=3
FLASHTYPE=READWRITE_A
FLASH_ERASE=20
FLASH_READ=1
FLASH_WRITE=20
IDLOC=8000-8003
IDLOCPROG=1,1,1
LINEARBASE=0x2000
MAKE=MICROCHIP
OSCCON=99
PAGESIZE=0x800
PCBITS=0xF
PROCID=1454
RAMBANK=20-7F,A0-EF,120-16F,1A0-1EF,220-26F,2A0-2EF,320-36F,3A0-3EF,420-46F,4A0-4EF,520-56F,5A0-5EF,620-64F
ROMSIZE=2000
SFR=INDF0,0,8
SFR=INDF1,1,8
SFR=PCL,2,8
SFR=STATUS,3,8
SFR=FSR0,4,16
SFR=FSR0L,4,8
SFR=FSR0H,5,8
SFR=FSR1,6,16
SFR=FSR1L,6,8
SFR=FSR1H,7,8
SFR=BSR,8,8
SFR=WREG,9,8
SFR=PCLATH,A,8
SFR=INTCON,B,8
SFR=PORTA,C,8
SFR=PORTC,E,8
SFR=PIR1,11,8
SFR=PIR2,12,8
SFR=TMR0,15,8
SFR=TMR1,16,16
SFR=TMR1L,16,8
SFR=TMR1H,17,8
SFR=T1CON,18,8
SFR=T1GCON,19,8
SFR=TMR2,1A,8
SFR=PR2,1B,8
SFR=T2CON,1C,8
SFR=TRISA,8C,8
SFR=TRISC,8E,8
SFR=PIE1,91,8
SFR=PIE2,92,8
SFR=OPTION_REG,95,8
SFR=PCON,96,8
SFR=WDTCON,97,8
SFR=OSCTUNE,98,8
SFR=OSCCON,99,8
SFR=OSCSTAT,9A,8
SFR=LATA,10C,8
SFR=LATC,10E,8
SFR=BORCON,116,8
SFR=FVRCON,117,8
SFR=APFCON,11D,8
SFR=ANSELA,18C,8
SFR=ANSELC,18E,8
SFR=PMADR,191,16
SFR=PMADRL,191,8
SFR=PMADRH,192,8
SFR=PMDAT,193,16
SFR=PMDATL,193,8
SFR=PMDATH,194,8
SFR=PMCON1,195,8
SFR=PMCON2,196,8
SFR=VREGCON,197,8
SFR=RCREG,199,8
SFR=TXREG,19A,8
SFR=SPBRG,19B,16
SFR=SPBRGL,19B,8
SFR=SPBRGH,19C,8
SFR=RCSTA,19D,8
SFR=TXSTA,19E,8
SFR=BAUDCON,19F,8
SFR=WPUA,20C,8
SFR=SSP1BUF,211,8
SFR=SSPBUF,211,8
SFR=SSP1ADD,212,8
SFR=SSPADD,212,8
SFR=SSP1MSK,213,8
SFR=SSPMSK,213,8
SFR=SSP1STAT,214,8
SFR=SSPSTAT,214,8
SFR=SSP1CON1,215,8
SFR=SSPCON,215,8
SFR=SSPCON1,215,8
SFR=SSP1CON2,216,8
SFR=SSPCON2,216,8
SFR=SSP1CON3,217,8
SFR=SSPCON3,217,8
SFR=IOCAP,391,8
SFR=IOCAN,392,8
SFR=IOCAF,393,8
SFR=CLKRCON,39A,8
SFR=ACTCON,39B,8
SFR=PWM1DCL,611,8
SFR=PWM1DCH,612,8
SFR=PWM1CON,613,8
SFR=PWM1CON0,613,8
SFR=PWM2DCL,614,8
SFR=PWM2DCH,615,8
SFR=PWM2CON,616,8
SFR=PWM2CON0,616,8
SFR=UCON,E8E,8
SFR=USTAT,E8F,8
SFR=UIR,E90,8
SFR=UCFG,E91,8
SFR=UIE,E92,8
SFR=UEIR,E93,8
SFR=UFRM,E94,16
SFR=UFRMH,E94,8
SFR=UFRML,E95,8
SFR=UADDR,E96,8
SFR=UEIE,E97,8
SFR=UEP0,E98,8
SFR=UEP1,E99,8
SFR=UEP2,E9A,8
SFR=UEP3,E9B,8
SFR=UEP4,E9C,8
SFR=UEP5,E9D,8
SFR=UEP6,E9E,8
SFR=UEP7,E9F,8
SFR=STATUS_SHAD,FE4,8
SFR=WREG_SHAD,FE5,8
SFR=BSR_SHAD,FE6,8
SFR=PCLATH_SHAD,FE7,8
SFR=FSR0L_SHAD,FE8,8
SFR=FSR0H_SHAD,FE9,8
SFR=FSR1L_SHAD,FEA,8
SFR=FSR1H_SHAD,FEB,8
SFR=STKPTR,FED,8
SFR=TOSL,FEE,8
SFR=TOSH,FEF,8
SFRFLD=INDF0,0,0,8
SFRFLD=INDF1,1,0,8
SFRFLD=PCL,2,0,8
SFRFLD=C,3,0,1
SFRFLD=DC,3,1,1
SFRFLD=Z,3,2,1
SFRFLD=nPD,3,3,1
SFRFLD=nTO,3,4,1
SFRFLD=CARRY,3,0,1
SFRFLD=ZERO,3,2,1
SFRFLD=FSR0L,4,0,8
SFRFLD=FSR0H,5,0,8
SFRFLD=FSR1L,6,0,8
SFRFLD=FSR1H,7,0,8
SFRFLD=BSR,8,0,5
SFRFLD=BSR0,8,0,1
SFRFLD=BSR1,8,1,1
SFRFLD=BSR2,8,2,1
SFRFLD=BSR3,8,3,1
SFRFLD=BSR4,8,4,1
SFRFLD=WREG0,9,0,8
SFRFLD=PCLATH,A,0,7
SFRFLD=IOCIF,B,0,1
SFRFLD=INTF,B,1,1
SFRFLD=TMR0IF,B,2,1
SFRFLD=IOCIE,B,3,1
SFRFLD=INTE,B,4,1
SFRFLD=TMR0IE,B,5,1
SFRFLD=PEIE,B,6,1
SFRFLD=GIE,B,7,1
SFRFLD=T0IF,B,2,1
SFRFLD=T0IE,B,5,1
SFRFLD=RA0,C,0,1
SFRFLD=RA1,C,1,1
SFRFLD=RA3,C,3,1
SFRFLD=RA4,C,4,1
SFRFLD=RA5,C,5,1
SFRFLD=RC0,E,0,1
SFRFLD=RC1,E,1,1
SFRFLD=RC2,E,2,1
SFRFLD=RC3,E,3,1
SFRFLD=RC4,E,4,1
SFRFLD=RC5,E,5,1
SFRFLD=TMR1IF,11,0,1
SFRFLD=TMR2IF,11,1,1
SFRFLD=SSP1IF,11,3,1
SFRFLD=TXIF,11,4,1
SFRFLD=RCIF,11,5,1
SFRFLD=TMR1GIF,11,7,1
SFRFLD=ACTIF,12,1,1
SFRFLD=USBIF,12,2,1
SFRFLD=BCL1IF,12,3,1
SFRFLD=OSFIF,12,7,1
SFRFLD=TMR0,15,0,8
SFRFLD=TMR1,16,0,16
SFRFLD=TMR1L,16,0,8
SFRFLD=TMR1H,17,0,8
SFRFLD=TMR1ON,18,0,1
SFRFLD=nT1SYNC,18,2,1
SFRFLD=T1OSCEN,18,3,1
SFRFLD=T1CKPS,18,4,2
SFRFLD=TMR1CS,18,6,2
SFRFLD=T1CKPS0,18,4,1
SFRFLD=T1CKPS1,18,5,1
SFRFLD=TMR1CS0,18,6,1
SFRFLD=TMR1CS1,18,7,1
SFRFLD=T1GSS,19,0,2
SFRFLD=T1GVAL,19,2,1
SFRFLD=T1GGO_nDONE,19,3,1
SFRFLD=T1GSPM,19,4,1
SFRFLD=T1GTM,19,5,1
SFRFLD=T1GPOL,19,6,1
SFRFLD=TMR1GE,19,7,1
SFRFLD=T1GSS0,19,0,1
SFRFLD=T1GSS1,19,1,1
SFRFLD=TMR2,1A,0,8
SFRFLD=PR2,1B,0,8
SFRFLD=T2CKPS,1C,0,2
SFRFLD=TMR2ON,1C,2,1
SFRFLD=T2OUTPS,1C,3,4
SFRFLD=T2CKPS0,1C,0,1
SFRFLD=T2CKPS1,1C,1,1
SFRFLD=T2OUTPS0,1C,3,1
SFRFLD=T2OUTPS1,1C,4,1
SFRFLD=T2OUTPS2,1C,5,1
SFRFLD=T2OUTPS3,1C,6,1
SFRFLD=TRISA4,8C,4,1
SFRFLD=TRISA5,8C,5,1
SFRFLD=TRISC0,8E,0,1
SFRFLD=TRISC1,8E,1,1
SFRFLD=TRISC2,8E,2,1
SFRFLD=TRISC3,8E,3,1
SFRFLD=TRISC4,8E,4,1
SFRFLD=TRISC5,8E,5,1
SFRFLD=TMR1IE,91,0,1
SFRFLD=TMR2IE,91,1,1
SFRFLD=SSP1IE,91,3,1
SFRFLD=TXIE,91,4,1
SFRFLD=RCIE,91,5,1
SFRFLD=TMR1GIE,91,7,1
SFRFLD=ACTIE,92,1,1
SFRFLD=USBIE,92,2,1
SFRFLD=BCL1IE,92,3,1
SFRFLD=OSFIE,92,7,1
SFRFLD=PS,95,0,3
SFRFLD=PSA,95,3,1
SFRFLD=TMR0SE,95,4,1
SFRFLD=TMR0CS,95,5,1
SFRFLD=INTEDG,95,6,1
SFRFLD=nWPUEN,95,7,1
SFRFLD=PS0,95,0,1
SFRFLD=PS1,95,1,1
SFRFLD=PS2,95,2,1
SFRFLD=T0SE,95,4,1
SFRFLD=T0CS,95,5,1
SFRFLD=nBOR,96,0,1
SFRFLD=nPOR,96,1,1
SFRFLD=nRI,96,2,1
SFRFLD=nRMCLR,96,3,1
SFRFLD=nRWDT,96,4,1
SFRFLD=STKUNF,96,6,1
SFRFLD=STKOVF,96,7,1
SFRFLD=SWDTEN,97,0,1
SFRFLD=WDTPS,97,1,5
SFRFLD=WDTPS0,97,1,1
SFRFLD=WDTPS1,97,2,1
SFRFLD=WDTPS2,97,3,1
SFRFLD=WDTPS3,97,4,1
SFRFLD=WDTPS4,97,5,1
SFRFLD=TUN,98,0,7
SFRFLD=TUN0,98,0,1
SFRFLD=TUN1,98,1,1
SFRFLD=TUN2,98,2,1
SFRFLD=TUN3,98,3,1
SFRFLD=TUN4,98,4,1
SFRFLD=TUN5,98,5,1
SFRFLD=TUN6,98,6,1
SFRFLD=SCS,99,0,2
SFRFLD=IRCF,99,2,4
SFRFLD=SPLLMULT,99,6,1
SFRFLD=SPLLEN,99,7,1
SFRFLD=SCS0,99,0,1
SFRFLD=SCS1,99,1,1
SFRFLD=IRCF0,99,2,1
SFRFLD=IRCF1,99,3,1
SFRFLD=IRCF2,99,4,1
SFRFLD=IRCF3,99,5,1
SFRFLD=HFIOFS,9A,0,1
SFRFLD=LFIOFR,9A,1,1
SFRFLD=HFIOFR,9A,4,1
SFRFLD=OSTS,9A,5,1
SFRFLD=PLLRDY,9A,6,1
SFRFLD=SOSCR,9A,7,1
SFRFLD=LATA4,10C,4,1
SFRFLD=LATA5,10C,5,1
SFRFLD=LATC0,10E,0,1
SFRFLD=LATC1,10E,1,1
SFRFLD=LATC2,10E,2,1
SFRFLD=LATC3,10E,3,1
SFRFLD=LATC4,10E,4,1
SFRFLD=LATC5,10E,5,1
SFRFLD=BORRDY,116,0,1
SFRFLD=BORFS,116,6,1
SFRFLD=SBOREN,116,7,1
SFRFLD=FVRRDY,117,6,1
SFRFLD=FVREN,117,7,1
SFRFLD=P2SEL,11D,2,1
SFRFLD=T1GSEL,11D,3,1
SFRFLD=SSSEL,11D,5,1
SFRFLD=SDOSEL,11D,6,1
SFRFLD=CLKRSEL,11D,7,1
SFRFLD=ANSELA,18C,0,8
SFRFLD=ANSC0,18E,0,1
SFRFLD=ANSC1,18E,1,1
SFRFLD=ANSC2,18E,2,1
SFRFLD=ANSC3,18E,3,1
SFRFLD=ANSELC,18E,0,8
SFRFLD=PMADRL,191,0,8
SFRFLD=PMADRH,192,0,7
SFRFLD=PMDATL,193,0,8
SFRFLD=PMDATH,194,0,6
SFRFLD=RD,195,0,1
SFRFLD=WR,195,1,1
SFRFLD=WREN,195,2,1
SFRFLD=WRERR,195,3,1
SFRFLD=FREE,195,4,1
SFRFLD=LWLO,195,5,1
SFRFLD=CFGS,195,6,1
SFRFLD=PMCON2,196,0,8
SFRFLD=VREGPM,197,0,2
SFRFLD=VREGPM0,197,0,1
SFRFLD=VREGPM1,197,1,1
SFRFLD=RCREG,199,0,8
SFRFLD=TXREG,19A,0,8
SFRFLD=SPBRGL,19B,0,8
SFRFLD=SPBRGH,19C,0,8
SFRFLD=RX9D,19D,0,1
SFRFLD=OERR,19D,1,1
SFRFLD=FERR,19D,2,1
SFRFLD=ADDEN,19D,3,1
SFRFLD=CREN,19D,4,1
SFRFLD=SREN,19D,5,1
SFRFLD=RX9,19D,6,1
SFRFLD=SPEN,19D,7,1
SFRFLD=TX9D,19E,0,1
SFRFLD=TRMT,19E,1,1
SFRFLD=BRGH,19E,2,1
SFRFLD=SENDB,19E,3,1
SFRFLD=SYNC,19E,4,1
SFRFLD=TXEN,19E,5,1
SFRFLD=TX9,19E,6,1
SFRFLD=CSRC,19E,7,1
SFRFLD=ABDEN,19F,0,1
SFRFLD=WUE,19F,1,1
SFRFLD=BRG16,19F,3,1
SFRFLD=SCKP,19F,4,1
SFRFLD=RCIDL,19F,6,1
SFRFLD=ABDOVF,19F,7,1
SFRFLD=WPUA3,20C,3,1
SFRFLD=WPUA4,20C,4,1
SFRFLD=WPUA5,20C,5,1
SFRFLD=WPUA,20C,0,6
SFRFLD=SSPBUF,211,0,8
SFRFLD=SSPADD,212,0,8
SFRFLD=SSPMSK,213,0,8
SFRFLD=BF,214,0,1
SFRFLD=UA,214,1,1
SFRFLD=R_nW,214,2,1
SFRFLD=S,214,3,1
SFRFLD=P,214,4,1
SFRFLD=D_nA,214,5,1
SFRFLD=CKE,214,6,1
SFRFLD=SMP,214,7,1
SFRFLD=SSP1M0,215,0,1
SFRFLD=SSP1M1,215,1,1
SFRFLD=SSP1M2,215,2,1
SFRFLD=SSP1M3,215,3,1
SFRFLD=CKP,215,4,1
SFRFLD=SSPEN,215,5,1
SFRFLD=SSPOV,215,6,1
SFRFLD=WCOL,215,7,1
SFRFLD=SSPM,215,0,4
SFRFLD=SSP1EN,215,5,1
SFRFLD=SSP1OV,215,6,1
SFRFLD=SEN,216,0,1
SFRFLD=RSEN,216,1,1
SFRFLD=PEN,216,2,1
SFRFLD=RCEN,216,3,1
SFRFLD=ACKEN,216,4,1
SFRFLD=ACKDT,216,5,1
SFRFLD=ACKSTAT,216,6,1
SFRFLD=GCEN,216,7,1
SFRFLD=DHEN,217,0,1
SFRFLD=AHEN,217,1,1
SFRFLD=SBCDE,217,2,1
SFRFLD=SDAHT,217,3,1
SFRFLD=BOEN,217,4,1
SFRFLD=SCIE,217,5,1
SFRFLD=PCIE,217,6,1
SFRFLD=ACKTIM,217,7,1
SFRFLD=IOCAP0,391,0,1
SFRFLD=IOCAP1,391,1,1
SFRFLD=IOCAP3,391,3,1
SFRFLD=IOCAP4,391,4,1
SFRFLD=IOCAP5,391,5,1
SFRFLD=IOCAP,391,0,6
SFRFLD=IOCAN0,392,0,1
SFRFLD=IOCAN1,392,1,1
SFRFLD=IOCAN3,392,3,1
SFRFLD=IOCAN4,392,4,1
SFRFLD=IOCAN5,392,5,1
SFRFLD=IOCAN,392,0,6
SFRFLD=IOCAF0,393,0,1
SFRFLD=IOCAF1,393,1,1
SFRFLD=IOCAF3,393,3,1
SFRFLD=IOCAF4,393,4,1
SFRFLD=IOCAF5,393,5,1
SFRFLD=IOCAF,393,0,6
SFRFLD=CLKRDIV,39A,0,3
SFRFLD=CLKRDC,39A,3,2
SFRFLD=CLKRSLR,39A,5,1
SFRFLD=CLKROE,39A,6,1
SFRFLD=CLKREN,39A,7,1
SFRFLD=CLKRDIV0,39A,0,1
SFRFLD=CLKRDIV1,39A,1,1
SFRFLD=CLKRDIV2,39A,2,1
SFRFLD=CLKRDC0,39A,3,1
SFRFLD=CLKRDC1,39A,4,1
SFRFLD=CLKRCD,39A,3,2
SFRFLD=ACTORS,39B,1,1
SFRFLD=ACTLOCK,39B,3,1
SFRFLD=ACTSRC,39B,4,1
SFRFLD=ACTUD,39B,6,1
SFRFLD=ACTEN,39B,7,1
SFRFLD=PWM1DCL,611,6,2
SFRFLD=PWM1DCL0,611,6,1
SFRFLD=PWM1DCL1,611,7,1
SFRFLD=PWM1DCH,612,0,8
SFRFLD=PWM1DCH0,612,0,1
SFRFLD=PWM1DCH1,612,1,1
SFRFLD=PWM1DCH2,612,2,1
SFRFLD=PWM1DCH3,612,3,1
SFRFLD=PWM1DCH4,612,4,1
SFRFLD=PWM1DCH5,612,5,1
SFRFLD=PWM1DCH6,612,6,1
SFRFLD=PWM1DCH7,612,7,1
SFRFLD=PWM1POL,613,4,1
SFRFLD=PWM1OUT,613,5,1
SFRFLD=PWM1OE,613,6,1
SFRFLD=PWM1EN,613,7,1
SFRFLD=PWM2DCL,614,6,2
SFRFLD=PWM2DCL0,614,6,1
SFRFLD=PWM2DCL1,614,7,1
SFRFLD=PWM2DCH,615,0,8
SFRFLD=PWM2DCH0,615,0,1
SFRFLD=PWM2DCH1,615,1,1
SFRFLD=PWM2DCH2,615,2,1
SFRFLD=PWM2DCH3,615,3,1
SFRFLD=PWM2DCH4,615,4,1
SFRFLD=PWM2DCH5,615,5,1
SFRFLD=PWM2DCH6,615,6,1
SFRFLD=PWM2DCH7,615,7,1
SFRFLD=PWM2POL,616,4,1
SFRFLD=PWM2OUT,616,5,1
SFRFLD=PWM2OE,616,6,1
SFRFLD=PWM2EN,616,7,1
SFRFLD=SUSPND,E8E,1,1
SFRFLD=RESUME,E8E,2,1
SFRFLD=USBEN,E8E,3,1
SFRFLD=PKTDIS,E8E,4,1
SFRFLD=SE0,E8E,5,1
SFRFLD=PPBRST,E8E,6,1
SFRFLD=PPBI,E8F,1,1
SFRFLD=DIR,E8F,2,1
SFRFLD=ENDP,E8F,3,4
SFRFLD=ENDP0,E8F,3,1
SFRFLD=ENDP1,E8F,4,1
SFRFLD=ENDP2,E8F,5,1
SFRFLD=ENDP3,E8F,6,1
SFRFLD=URSTIF,E90,0,1
SFRFLD=UERRIF,E90,1,1
SFRFLD=ACTVIF,E90,2,1
SFRFLD=TRNIF,E90,3,1
SFRFLD=IDLEIF,E90,4,1
SFRFLD=STALLIF,E90,5,1
SFRFLD=SOFIF,E90,6,1
SFRFLD=PPB,E91,0,2
SFRFLD=FSEN,E91,2,1
SFRFLD=UPUEN,E91,4,1
SFRFLD=UTEYE,E91,7,1
SFRFLD=PPB0,E91,0,1
SFRFLD=PPB1,E91,1,1
SFRFLD=URSTIE,E92,0,1
SFRFLD=UERRIE,E92,1,1
SFRFLD=ACTVIE,E92,2,1
SFRFLD=TRNIE,E92,3,1
SFRFLD=IDLEIE,E92,4,1
SFRFLD=STALLIE,E92,5,1
SFRFLD=SOFIE,E92,6,1
SFRFLD=PIDEF,E93,0,1
SFRFLD=CRC5EF,E93,1,1
SFRFLD=CRC16EF,E93,2,1
SFRFLD=DFN8EF,E93,3,1
SFRFLD=BTOEF,E93,4,1
SFRFLD=BTSEF,E93,7,1
SFRFLD=FRM8,E94,0,1
SFRFLD=FRM9,E94,1,1
SFRFLD=FRM10,E94,2,1
SFRFLD=FRM0,E95,0,1
SFRFLD=FRM1,E95,1,1
SFRFLD=FRM2,E95,2,1
SFRFLD=FRM3,E95,3,1
SFRFLD=FRM4,E95,4,1
SFRFLD=FRM5,E95,5,1
SFRFLD=FRM6,E95,6,1
SFRFLD=FRM7,E95,7,1
SFRFLD=ADDR0,E96,0,1
SFRFLD=ADDR1,E96,1,1
SFRFLD=ADDR2,E96,2,1
SFRFLD=ADDR3,E96,3,1
SFRFLD=ADDR4,E96,4,1
SFRFLD=ADDR5,E96,5,1
SFRFLD=ADDR6,E96,6,1
SFRFLD=PIDEE,E97,0,1
SFRFLD=CRC5EE,E97,1,1
SFRFLD=CRC16EE,E97,2,1
SFRFLD=DFN8EE,E97,3,1
SFRFLD=BTOEE,E97,4,1
SFRFLD=BTSEE,E97,7,1
SFRFLD=EPSTALL,E98,0,1
SFRFLD=EPINEN,E98,1,1
SFRFLD=EPOUTEN,E98,2,1
SFRFLD=EPCONDIS,E98,3,1
SFRFLD=EPHSHK,E98,4,1
SFRFLD=EPSTALL,E99,0,1
SFRFLD=EPINEN,E99,1,1
SFRFLD=EPOUTEN,E99,2,1
SFRFLD=EPCONDIS,E99,3,1
SFRFLD=EPHSHK,E99,4,1
SFRFLD=EPSTALL,E9A,0,1
SFRFLD=EPINEN,E9A,1,1
SFRFLD=EPOUTEN,E9A,2,1
SFRFLD=EPCONDIS,E9A,3,1
SFRFLD=EPHSHK,E9A,4,1
SFRFLD=EPSTALL,E9B,0,1
SFRFLD=EPINEN,E9B,1,1
SFRFLD=EPOUTEN,E9B,2,1
SFRFLD=EPCONDIS,E9B,3,1
SFRFLD=EPHSHK,E9B,4,1
SFRFLD=EPSTALL,E9C,0,1
SFRFLD=EPINEN,E9C,1,1
SFRFLD=EPOUTEN,E9C,2,1
SFRFLD=EPCONDIS,E9C,3,1
SFRFLD=EPHSHK,E9C,4,1
SFRFLD=EPSTALL,E9D,0,1
SFRFLD=EPINEN,E9D,1,1
SFRFLD=EPOUTEN,E9D,2,1
SFRFLD=EPCONDIS,E9D,3,1
SFRFLD=EPHSHK,E9D,4,1
SFRFLD=EPSTALL,E9E,0,1
SFRFLD=EPINEN,E9E,1,1
SFRFLD=EPOUTEN,E9E,2,1
SFRFLD=EPCONDIS,E9E,3,1
SFRFLD=EPHSHK,E9E,4,1
SFRFLD=EPSTALL,E9F,0,1
SFRFLD=EPINEN,E9F,1,1
SFRFLD=EPOUTEN,E9F,2,1
SFRFLD=EPCONDIS,E9F,3,1
SFRFLD=EPHSHK,E9F,4,1
SFRFLD=C,FE4,0,1
SFRFLD=DC,FE4,1,1
SFRFLD=Z,FE4,2,1
SFRFLD=WREG_SHAD,FE5,0,8
SFRFLD=BSR_SHAD,FE6,0,5
SFRFLD=PCLATH_SHAD,FE7,0,7
SFRFLD=FSR0L_SHAD,FE8,0,8
SFRFLD=FSR0H_SHAD,FE9,0,8
SFRFLD=FSR1L_SHAD,FEA,0,8
SFRFLD=FSR1H_SHAD,FEB,0,8
SFRFLD=STKPTR,FED,0,5
SFRFLD=TOSL,FEE,0,8
SFRFLD=TOSH,FEF,0,7
STACKDEPTH=10
VOLSFRS=196-196,F8C-F8E,F90-F91,FE3-FEB,FED-FEF